Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Altera I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) * This is Altera's synthesizable logic block I2C Controller for use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) * in Altera's FPGAs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - compatible : should be "altr,softip-i2c-v1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - reg        : Offset and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  - interrupts : <IRQ> where IRQ is the interrupt number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  - clocks     : phandle to input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Recommended properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clock-frequency : desired I2C bus clock frequency in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  - fifo-size : Size of the RX and TX FIFOs in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  - Child nodes conforming to i2c bus binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	i2c@100080000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		compatible = "altr,softip-i2c-v1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		reg = <0x00000001 0x00080000 0x00000040>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		interrupts = <0 43 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&clk_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clock-frequency = <100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		fifo-size = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		eeprom@51 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			compatible = "atmel,24c32";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			reg = <0x51>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			pagesize = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)