Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controller can support upto 16 Fan tachometer inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) There can be upto 8 fans supported. Each fan can have one PWM output and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) one/two Fan tach inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties for pwm-tacho node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #address-cells : should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #size-cells : should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #cooling-cells: should be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg : address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - pinctrl-names : a pinctrl state named "default" must be defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - pinctrl-0 : phandle referencing pin configuration of the PWM ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	       "aspeed,ast2500-pwm-tacho" for AST2500.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clocks : phandle to clock provider with the clock number in the second cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - resets : phandle to reset controller with the reset number in the second cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) fan subnode format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Under fan subnode there can upto 8 child nodes, with each child node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) representing a fan. If there are 8 fans each fan can have one PWM port and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) one/two Fan tach inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) For PWM port can be configured cooling-levels to create cooling device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Cooling device could be bound to a thermal zone for the thermal control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Required properties for each child node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - reg : should specify PWM source port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	integer value in the range 0 to 7 with 0 indicating PWM port A and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	7 indicating PWM port H.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - cooling-levels: PWM duty cycle values in a range from 0 to 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)                   which correspond to thermal cooling states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - aspeed,fan-tach-ch : should specify the Fan tach input channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)                 integer value in the range 0 through 15, with 0 indicating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		Fan tach channel 0 and 15 indicating Fan tach channel 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		Atleast one Fan tach input channel is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) pwm_tacho: pwmtachocontroller@1e786000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	#cooling-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	reg = <0x1E786000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	compatible = "aspeed,ast2500-pwm-tacho";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	clocks = <&syscon ASPEED_CLK_APB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	resets = <&syscon ASPEED_RESET_PWM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	fan@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		reg = <0x00>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	fan@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		reg = <0x01>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };