^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) SPRD Hardware Spinlock Device Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) -------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : should be "sprd,hwspinlock-r3p0".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg : the register address of hwspinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - #hwlock-cells : hwlock users only use the hwlock id to represent a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) hwlock, so the number of cells should be <1> here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - clock-names : Must contain "enable".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks : Must contain a phandle entry for the clock in clock-names, see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) common clock bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Please look at the generic hwlock binding for usage information for consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "Documentation/devicetree/bindings/hwlock/hwlock.txt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example of hwlock provider:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) hwspinlock@40500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "sprd,hwspinlock-r3p0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0 0x40500000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #hwlock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clock-names = "enable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) clocks = <&clk_aon_apb_gates0 22>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };