Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) GPIO controller on CE4100 / Sodaville SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ==========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The bindings for CE4100's GPIO controller match the generic description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) which is covered by the gpio.txt file in this folder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) The only additional property is the intel,muxctl property which holds the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) value which is written into the MUXCNTL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) There is no compatible property for now because the driver is probed via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) PCI id (vendor 0x8086 device 0x2e67).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The interrupt specifier consists of two cells encoded as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - <1st cell>: The interrupt-number that identifies the interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - <2nd cell>: The level-sense information, encoded as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		4 - active high level-sensitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		8 - active low level-sensitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example of the GPIO device and one user:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	pcigpio: gpio@b,1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			/* two cells for GPIO and interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			compatible = "pci8086,2e67.2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 					   "pci8086,2e67",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 					   "pciclassff0000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 					   "pciclassff00";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			reg = <0x15900 0x0 0x0 0x0 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			/* Interrupt line of the gpio device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			interrupts = <15 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			/* It is an interrupt and GPIO controller itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			intel,muxctl = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	testuser@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			compatible = "example,testuser";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			/* User the 11th GPIO line as an active high triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			 * level interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			interrupts = <11 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			interrupt-parent = <&pcigpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			/* Use this GPIO also with the gpio functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			gpios = <&pcigpio 11 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	};