Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Aspeed SGPIO controller Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) --------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) support the following options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - Support interrupt option for each input port and various interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   sensitivity option (level-high, level-low, edge-high, edge-low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - Support reset tolerance option for each output port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Directly connected to APB bus and its shift clock is from APB bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   divided by a programmable value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - Co-work with external signal-chained TTL components (74LV165/74LV595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - compatible : Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #gpio-cells : Should be 2, see gpio.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg : Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - gpio-controller : Marks the device node as a GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - interrupt-controller : Mark the GPIO controller as an interrupt-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   output. Up to 80 pins, must be a multiple of 8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - clocks : A phandle to the APB clock for SGPM clock division
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - bus-frequency : SGPM CLK frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) The sgpio and interrupt properties are further described in their respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bindings documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - Documentation/devicetree/bindings/gpio/gpio.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	sgpio: sgpio@1e780200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		compatible = "aspeed,ast2500-sgpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		interrupts = <40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		reg = <0x1e780200 0x0100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		clocks = <&syscon ASPEED_CLK_APB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		ngpios = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		bus-frequency = <12000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	};