Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx Zynq GPIO controller Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - #gpio-cells 		: Should be two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 			  - First cell is the GPIO line number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 			  - Second cell is used to specify optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 			    parameters (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - compatible		: Should be "xlnx,zynq-gpio-1.0" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 			  "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			  or "xlnx,pmc-gpio-1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks		: Clock specifier (see clock bindings for details)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - gpio-controller	: Marks the device node as a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupts		: Interrupt specifier (see interrupt bindings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			  details)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupt-controller	: Marks the device node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - #interrupt-cells 	: Should be 2.  The first cell is the GPIO number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			  The second cell bits[3:0] is used to specify trigger type and level flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			      1 = low-to-high edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			      2 = high-to-low edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			      4 = active high level-sensitive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			      8 = active low level-sensitive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - reg			: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	gpio@e000a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		compatible = "xlnx,zynq-gpio-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clocks = <&clkc 42>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		interrupts = <0 20 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		reg = <0xe000a000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	};