^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) APM X-Gene SoC GPIO controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This is a gpio controller that is part of the flash controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) This gpio controller controls a total of 48 gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible: "apm,xgene-gpio" for X-Gene GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - reg: Physical base address and size of the controller's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #gpio-cells: Should be two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - first cell is the pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - second cell is used to specify the gpio polarity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 0 = active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 1 = active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - gpio-controller: Marks the device node as a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) gpio0: gpio0@1701c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "apm,xgene-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0x0 0x1701c000 0x0 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };