Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) APM X-Gene Standby GPIO controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This is a gpio controller in the standby domain. It also supports interrupt in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) some particular pins which are sourced to its parent interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) as diagram below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)                             +-----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)                             | X-Gene standby  |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)                             | GPIO controller +------ GPIO_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) +------------+              |                 | ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) | Parent IRQ | EXT_INT_0    |                 +------ GPIO_8/EXT_INT_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) | controller | (SPI40)      |                 | ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) | (GICv2)    +--------------+                 +------ GPIO_[N+8]/EXT_INT_N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) |            |   ...        |                 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) |            | EXT_INT_N    |                 +------ GPIO_[N+9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) |            | (SPI[40 + N])|                 | ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) |            +--------------+                 +------ GPIO_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) +------------+              +-----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: Physical base address and size of the controller's registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - #gpio-cells: Should be two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	- first cell is the pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	- second cell is used to specify the gpio polarity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		0 = active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		1 = active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - gpio-controller: Marks the device node as a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - interrupt-cells: Should be two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)        - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)        - second cell is used to specify flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - interrupt-controller: Marks the device node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - apm,nr-gpios: Optional, specify number of gpios pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - apm,nr-irqs: Optional, specify number of interrupt pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - apm,irq-start: Optional, specify lowest gpio pin support interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	sbgpio: gpio@17001000{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		compatible = "apm,xgene-gpio-sb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		reg = <0x0 0x17001000 0x0 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		interrupts = 	<0x0 0x28 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				<0x0 0x29 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 				<0x0 0x2a 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				<0x0 0x2b 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				<0x0 0x2c 0x1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 				<0x0 0x2d 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		apm,nr-gpios = <22>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		apm,nr-irqs = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		apm,irq-start = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	testuser {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		compatible = "example,testuser";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		/* Use the GPIO_13/EXT_INT_5 line as an active high triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		 * level interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		interrupts = <5 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		interrupt-parent = <&sbgpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	};