Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Freescale VF610 PORT/GPIO module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - Stefan Agner <stefan@agner.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   each, and each PORT module has its own interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   Note: Each GPIO port should have an alias correctly numbered in "aliases"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       - const: fsl,vf610-gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)           - const: fsl,imx7ulp-gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)           - const: fsl,vf610-gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)     description: The first reg tuple represents the PORT module, the second tuple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)       represents the GPIO module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   interrupt-controller: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   "#interrupt-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)     const: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   "#gpio-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)     const: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   gpio-controller: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)       - description: SoC GPIO clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)       - description: SoC PORT clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)       - const: gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)       - const: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   gpio-ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)   - interrupt-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   - "#interrupt-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)   - "#gpio-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   - gpio-controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)     gpio1: gpio@40049000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)         compatible = "fsl,vf610-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)         reg = <0x40049000 0x1000>, <0x400ff000 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)         gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)         #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)         interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)         #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)         gpio-ranges = <&iomuxc 0 0 32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)     };