^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * TS-4800 FPGA's GPIO controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Must be "technologic,ts4800-gpio".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - #gpio-cells: Should be two. The first cell is the pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg: Physical base address of the controller and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) of memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Optional property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - ngpios: See "gpio.txt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) gpio1: gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) compatible = "technologic,ts4800-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) reg = <0x10020 0x6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ngpios = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };