Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Lantiq SoC Serial To Parallel (STP) GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) peripheral controller used to drive external shift register cascades. At most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) to drive the 2 LSBs of the cascade automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible : Should be "lantiq,gpio-stp-xway"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg : Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #gpio-cells : Should be two.  The first cell is the pin number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   the second cell is used to specify optional parameters (currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   unused).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - gpio-controller : Marks the device node as a gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - lantiq,shadow : The default value that we shall assume as already set on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   shift register cascade.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   in the shift register cascade.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   property can enable this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - lantiq,rising : use rising instead of falling edge for the shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) gpio1: stp@e100bb0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	compatible = "lantiq,gpio-stp-xway";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reg = <0xE100BB0 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	lantiq,shadow = <0xffff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	lantiq,groups = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	lantiq,dsl = <0x3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	lantiq,phy1 = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	lantiq,phy2 = <0x7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* lantiq,rising; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };