Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * PCF857x-compatible I/O expanders
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) driven high by a pull-up current source or driven low to ground. This combines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) the direction and output level into a single bit per line, which can't be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) back. We can't actually know at initialization time whether a line is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) (a) as output and driving the signal low/high, or (b) as input and reporting a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) low/high value, without knowing the last value written since the chip came out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) of reset (if any). The only reliable solution for setting up line direction is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) thus to do it explicitly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)     - "maxim,max7328": For the Maxim MAX7378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)     - "maxim,max7329": For the Maxim MAX7329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)     - "nxp,pca8574": For the NXP PCA8574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     - "nxp,pca8575": For the NXP PCA8575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     - "nxp,pca9670": For the NXP PCA9670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     - "nxp,pca9671": For the NXP PCA9671
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     - "nxp,pca9672": For the NXP PCA9672
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     - "nxp,pca9673": For the NXP PCA9673
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)     - "nxp,pca9674": For the NXP PCA9674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)     - "nxp,pca9675": For the NXP PCA9675
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     - "nxp,pcf8574": For the NXP PCF8574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     - "nxp,pcf8574a": For the NXP PCF8574A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     - "nxp,pcf8575": For the NXP PCF8575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   - reg: I2C slave address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   - gpio-controller: Marks the device node as a gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)     cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   - lines-initial-states: Bitmask that specifies the initial state of each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)   line. When a bit is set to zero, the corresponding line will be initialized to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   the input (pulled-up) state. When the  bit is set to one, the line will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   initialized the low-level output state. If the property is not specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   all lines will be initialized to the input state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   The I/O expander can detect input state changes, and thus optionally act as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   an interrupt controller. When the expander interrupt line is connected all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)   following properties must be set. For more information please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)   interrupt controller device tree bindings documentation available at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)   - interrupt-controller: Identifies the node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)   - interrupts: Interrupt specifier for the controllers interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Please refer to gpio.txt in this directory for details of the common GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bindings used by client devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Example: PCF8575 I/O expander node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	pcf8575: gpio@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		compatible = "nxp,pcf8575";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		reg = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		interrupt-parent = <&irqpin2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		interrupts = <3 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	};