^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Marvell EBU GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) should be used for the Discovery MV78200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) (MV78230, MV78260, MV78460).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) SoCs (either from AP or CP), see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) for specific details about the offset property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - reg: Address and length of the register set for the device. Only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) entry is expected, except for the "marvell,armadaxp-gpio" variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) for which two entries are expected: one for the general registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - interrupts: The list of interrupts that are used for all the pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) managed by this GPIO bank. There can be more than one interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (example: 1 interrupt per 8 pins on Armada XP, which means 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) interrupts per bank of 32 GPIOs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - interrupt-controller: identifies the node as an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - #interrupt-cells: specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) interrupt source. Should be two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) The first cell is the GPIO number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) The second cell is used to specify flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bits[3:0] trigger type and level flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 1 = low-to-high edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2 = high-to-low edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 4 = active high level-sensitive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 8 = active low level-sensitive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - gpio-controller: marks the device node as a gpio controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - ngpios: number of GPIOs this controller has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - #gpio-cells: Should be two. The first cell is the pin number. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) second cell is reserved for flags, unused at the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) In order to use the GPIO lines in PWM mode, some additional optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) properties are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - compatible: Must contain "marvell,armada-370-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - reg: an additional register set is needed, for the GPIO Blink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Counter on/off registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - reg-names: Must contain an entry "pwm" corresponding to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) additional register range needed for PWM operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - #pwm-cells: Should be two. The first cell is the GPIO line number. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) second cell is the period in nanoseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - clocks: Must be a phandle to the clock for the GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gpio0: gpio@d0018100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) compatible = "marvell,armadaxp-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg = <0xd0018100 0x40>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <0xd0018800 0x30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ngpios = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) interrupts = <16>, <17>, <18>, <19>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) gpio1: gpio@18140 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "marvell,armada-370-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = <0x18140 0x40>, <0x181c8 0x08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg-names = "gpio", "pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ngpios = <17>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #pwm-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupts = <87>, <88>, <89>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clocks = <&coreclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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