Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : Should be "fsl,<soc>-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   The following <soc>s are known to be supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	ls1021a, ls1043a, ls2080a, ls1028a, ls1088a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg : Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - interrupts : Should be the port interrupt shared by all 32 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #gpio-cells : Should be two.  The first cell is the pin number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   the second cell is used to specify the gpio polarity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)       0 = active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)       1 = active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - little-endian : GPIO registers are used as little endian. If not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                   present registers are used as big endian by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example of gpio-controller node for a mpc5125 SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) gpio0: gpio@1100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	compatible = "fsl,mpc5125-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	reg = <0x1100 0x080>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	interrupts = <78 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example of gpio-controller node for a ls2080a SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) gpio0: gpio@2300000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reg = <0x0 0x2300000 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	interrupts = <0 36 0x4>; /* Level high type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	little-endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example of gpio-controller node for a ls1028a/ls1088a SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) gpio1: gpio@2300000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	reg = <0x0 0x2300000 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	little-endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };