^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Spreadtrum EIC controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The EIC is the abbreviation of external interrupt controller, which can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) one is in digital chip, and another one is in PMIC. The digital chip EIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The EIC-debounce sub-module provides up to 8 source input signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) connections. A debounce mechanism is used to capture the input signals'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) stable status (millisecond resolution) and a single-trigger mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) is introduced into this sub-module to enhance the input event detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reliability. In addition, this sub-module's clock can be shut off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) automatically to reduce power dissipation. Moreover the debounce range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) is from 1ms to 4s with a step size of 1ms. The input signal will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ignored if it is asserted for less than 1 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The EIC-latch sub-module is used to latch some special power down signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) and generate interrupts, since the EIC-latch does not depend on the APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clock to capture signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) The EIC-async sub-module uses a 32kHz clock to capture the short signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) (microsecond resolution) to generate interrupts by level or edge trigger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) The EIC-sync is similar with GPIO's input function, which is a synchronized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) signal input register. It can generate interrupts by level or edge trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) when detecting input signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - compatible: Should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "sprd,sc9860-eic-debounce",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "sprd,sc9860-eic-latch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "sprd,sc9860-eic-async",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "sprd,sc9860-eic-sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "sprd,sc2731-eic".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - reg: Define the base and range of the I/O address space containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) the GPIO controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - gpio-controller: Marks the device node as a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - #gpio-cells: Should be <2>. The first cell is the gpio number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) the second cell is used to specify optional parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - interrupt-controller: Marks the device node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - #interrupt-cells: Should be <2>. Specifies the number of cells needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) to encode interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - interrupts: Should be the port interrupt shared by all the gpios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) eic_debounce: gpio@40210000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) compatible = "sprd,sc9860-eic-debounce";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg = <0 0x40210000 0 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) eic_latch: gpio@40210080 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) compatible = "sprd,sc9860-eic-latch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg = <0 0x40210080 0 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) eic_async: gpio@402100a0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) compatible = "sprd,sc9860-eic-async";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = <0 0x402100a0 0 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) eic_sync: gpio@402100c0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) compatible = "sprd,sc9860-eic-sync";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = <0 0x402100c0 0 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pmic_eic: gpio@300 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) compatible = "sprd,sc2731-eic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = <0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupt-parent = <&sc2731_pmic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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