^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Generic 8-bits shift register GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should contain one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "fairchild,74hc595"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "nxp,74lvc594"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg : chip select number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - gpio-controller : Marks the device node as a gpio controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #gpio-cells : Should be two. The first cell is the pin number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) the second cell is used to specify the gpio polarity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 0 = active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 1 = active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - registers-number: Number of daisy-chained shift registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - enable-gpios: GPIO connected to the OE (Output Enable) pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) gpio5: gpio5@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) compatible = "fairchild,74hc595";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) registers-number = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spi-max-frequency = <100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };