Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * General Purpose Input Output (GPIO) bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: "cavium,octeon-3860-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: The base address of the GPIO unit's register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - gpio-controller: This is a GPIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #gpio-cells: Must be <2>.  The first cell is the GPIO pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupt-controller: The GPIO controller is also an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   controller, many of its pins may be configured as an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #interrupt-cells: Must be <2>.  The first cell is the GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    connected to the interrupt source.  The second cell is the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    triggering protocol and may have one of four values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)    1 - edge triggered on the rising edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)    2 - edge triggered on the falling edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)    4 - level triggered active high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)    8 - level triggered active low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - interrupts: Interrupt routing for each pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	gpio-controller@1070000000800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "cavium,octeon-3860-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		reg = <0x10700 0x00000800 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		/* Interrupts are specified by two parts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		 * 1) GPIO pin number (0..15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		 * 2) Triggering (1 - edge rising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		 *		  2 - edge falling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		 *		  4 - level active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		 *		  8 - level active low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		/* The GPIO pin connect to 16 consecutive CUI bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			     <0 20>, <0 21>, <0 22>, <0 23>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			     <0 24>, <0 25>, <0 26>, <0 27>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			     <0 28>, <0 29>, <0 30>, <0 31>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};