Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx Zynq FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible:		should contain "xlnx,zynq-devcfg-1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg:			base address and size for memory mapped io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts:		interrupt for the FPGA manager device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks:		phandle for clocks required operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clock-names:		name for the clock, should be "ref_clk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - syscon:		phandle for access to SLCR registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	devcfg: devcfg@f8007000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		compatible = "xlnx,zynq-devcfg-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		reg = <0xf8007000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		interrupts = <0 8 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		clocks = <&clkc 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		clock-names = "ref_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		syscon = <&slcr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	};