Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx Slave Serial SPI FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) bitstream over what is referred to as "slave serial" interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) The slave serial link is not technically SPI, and might require extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) circuits in order to play nicely with other SPI slaves on the same bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) See:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - compatible: should contain "xlnx,fpga-slave-serial"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg: spi chip select of the FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - done-gpios: config status pin (referred to as DONE in the manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - init-b-gpios: initialization status and configuration error pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)                 (referred to as INIT_B in the manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example for full FPGA configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	fpga-region0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		compatible = "fpga-region";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		fpga-mgr = <&fpga_mgr_spi>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		#address-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		#size-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	spi1: spi@10680 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		pinctrl-0 = <&spi0_pins>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		cell-index = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		interrupts = <92>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		clocks = <&coreclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		fpga_mgr_spi: fpga-mgr@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			compatible = "xlnx,fpga-slave-serial";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			spi-max-frequency = <60000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			spi-cpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	};