Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Xilinx LogiCORE Partial Reconfig Decoupler Softcore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) decouplers / fpga bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) The controller can decouple/disable the bridges which prevents signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) changes from passing through the bridge.  The controller can also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) couple / enable the bridges which allows traffic to pass through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) bridge normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The Driver supports only MMIO handling. A PR region can have multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) PR Decouplers which can be handled independently or chained via decouple/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) decouple_status signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - compatible		: Should contain "xlnx,pr-decoupler-1.00" followed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)                           "xlnx,pr-decoupler"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - regs			: base address and size for decoupler module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clocks		: input clock to IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clock-names		: should contain "aclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) See Documentation/devicetree/bindings/fpga/fpga-region.txt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	fpga-bridge@100000450 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		compatible = "xlnx,pr-decoupler-1.00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			     "xlnx-pr-decoupler";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		regs = <0x10000045 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clocks = <&clkc 15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clock-names = "aclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		bridge-enable = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	};