^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Lattice MachXO2 Slave SPI FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Lattice MachXO2 FPGAs support a method of loading the bitstream over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) 'slave SPI' interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) See 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: should contain "lattice,machxo2-slave-spi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: spi chip select of the FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Example for full FPGA configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) fpga-region0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) compatible = "fpga-region";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) fpga-mgr = <&fpga_mgr_spi>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #address-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #size-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) spi1: spi@2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) fpga_mgr_spi: fpga-mgr@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) compatible = "lattice,machxo2-slave-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spi-max-frequency = <8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };