Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Lattice iCE40 FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible:		Should contain "lattice,ice40-fpga-mgr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg:			SPI chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - spi-max-frequency:	Maximum SPI frequency (>=1000000, <=25000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - cdone-gpios:		GPIO input connected to CDONE pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reset-gpios:		Active-low GPIO output connected to CRESET_B pin. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 			that unless the GPIO is held low during startup, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 			FPGA will enter Master SPI mode and drive SCK with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			clock signal potentially jamming other devices on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			bus until the firmware is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	fpga: fpga@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		compatible = "lattice,ice40-fpga-mgr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		spi-max-frequency = <1000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	};