^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) FPGA Region Device Tree Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Alan Tull 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) CONTENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - Terminology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - Sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - FPGA Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Supported Use Models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Device Tree Examples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - Constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Introduction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) This device tree binding document hits some of the high points of FPGA usage and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) attempts to include terminology used by both major FPGA manufacturers. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) document isn't a replacement for any manufacturers specifications for FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Terminology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Full Reconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The entire FPGA is programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Partial Reconfiguration (PR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * A section of an FPGA is reprogrammed while the rest of the FPGA is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) affected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Not all FPGA's support PR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Partial Reconfiguration Region (PRR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Also called a "reconfigurable partition"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * A PRR is a specific section of a FPGA reserved for reconfiguration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * A base (or static) FPGA image may create a set of PRR's that later may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) be independently reprogrammed many times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The size and specific location of each PRR is fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * The connections at the edge of each PRR are fixed. The image that is loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) into a PRR must fit and must use a subset of the region's connections.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * The busses within the FPGA are split such that each region gets its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) branch that may be gated independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Persona
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Also called a "partial bit stream"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * An FPGA image that is designed to be loaded into a PRR. There may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) any number of personas designed to fit into a PRR, but only one at at time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) may be loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * A persona may create more regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FPGA Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * FPGA Bridges gate bus signals between a host and FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * FPGA Bridges should be disabled while the FPGA is being programmed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) prevent spurious signals on the cpu bus and to the soft logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * FPGA bridges may be actual hardware or soft logic on an FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * During Full Reconfiguration, hardware bridges between the host and FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) will be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * During Partial Reconfiguration of a specific region, that region's bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) will be used to gate the busses. Traffic to other regions is not affected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * In some implementations, the FPGA Manager transparantly handles gating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) buses, eliminating the need to show the hardware FPGA bridges in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * An FPGA image may create a set of reprogrammable regions, each having its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) own bridge and its own split of the busses in the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * An FPGA Manager is a hardware block that programs an FPGA under the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) of a host processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Base Image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Also called the "static image"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * An FPGA image that is designed to do full reconfiguration of the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * A base image may set up a set of partial reconfiguration regions that may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) later be reprogrammed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ---------------- ----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) | Host CPU | | FPGA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) | ----| | ----------- -------- |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) | | H | | |==>| Bridge0 |<==>| PRR0 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) | | W | | | ----------- -------- |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) | | B |<=====>|<==| ----------- -------- |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) | | R | | |==>| Bridge1 |<==>| PRR1 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) | | I | | | ----------- -------- |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) | | D | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) | | G | | | ----------- -------- |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) | | E | | |==>| Bridge2 |<==>| PRR2 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) | ----| | ----------- -------- |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ---------------- ----------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Figure 1: An FPGA set up with a base image that created three regions. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) region (PRR0-2) gets its own split of the busses that is independently gated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reprogrammed independently while the rest of the system continues to function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) Sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) When a DT overlay that targets a FPGA Region is applied, the FPGA Region will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) do the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 1. Disable appropriate FPGA bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 2. Program the FPGA using the FPGA manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 3. Enable the FPGA bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 4. The Device Tree overlay is accepted into the live tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 5. Child devices are populated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) When the overlay is removed, the child nodes will be removed and the FPGA Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) will disable the bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FPGA Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Region brings together the elements needed to program on a running system and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) add the child devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * FPGA Bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * image-specific information needed to to the programming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * child nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FPGA while an operating system is running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) An FPGA Region that exists in the live Device Tree reflects the current state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) If the live tree shows a "firmware-name" property or child nodes under a FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Region, the FPGA already has been programmed. A DTO that targets a FPGA Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) and adds the "firmware-name" property is taken as a request to reprogram the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FPGA. After reprogramming is successful, the overlay is accepted into the live
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) The base FPGA Region in the device tree represents the FPGA and supports full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reconfiguration. It must include a phandle to an FPGA Manager. The base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FPGA region will be the child of one of the hardware bridges (the bridge that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) allows register access) between the cpu and the FPGA. If there are more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) one bridge to control during FPGA programming, the region will also contain a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) list of phandles to the additional hardware FPGA Bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) For partial reconfiguration (PR), each PR region will have an FPGA Region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) These FPGA regions are children of FPGA bridges which are then children of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) If an FPGA Region does not specify a FPGA Manager, it will inherit the FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) Manager specified by its ancestor FPGA Region. This supports both the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) where the same FPGA Manager is used for all of a FPGA as well the case where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) a different FPGA Manager is used for each region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) shutting down bridges that are upstream from the other active regions while one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) within the static image of the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) - compatible : should contain "fpga-region"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) - fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) inherit this property from their ancestor regions. A fpga-mgr property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) in a region will override any inherited FPGA manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) - #address-cells, #size-cells, ranges : must be present to handle address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mapping for child nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) - firmware-name : should contain the name of an FPGA image file located on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) firmware search path. If this property shows up in a live device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) it indicates that the FPGA has already been programmed with this image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) If this property is in an overlay targeting a FPGA region, it is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) request to program the FPGA with that image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) controlled during FPGA programming along with the parent FPGA bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) This property is optional if the FPGA Manager handles the bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) If the fpga-region is the child of a fpga-bridge, the list should not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) contain the parent bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) - partial-fpga-config : boolean, set if partial reconfiguration is to be done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) otherwise full reconfiguration is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) - external-fpga-config : boolean, set if the FPGA has already been configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) prior to OS boot up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) - encrypted-fpga-config : boolean, set if the bitstream is encrypted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) - region-unfreeze-timeout-us : The maximum time in microseconds to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bridges to successfully become enabled after the region has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) - region-freeze-timeout-us : The maximum time in microseconds to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bridges to successfully become disabled before the region has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) - config-complete-timeout-us : The maximum time in microseconds time for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FPGA to go to operating mode after the region has been programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) - child nodes : devices in the FPGA after programming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) In the example below, when an overlay is applied targeting fpga-region0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) fpga_mgr is used to program the FPGA. Two bridges are controlled during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) fpga-bridges property. During programming, these bridges are disabled, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) firmware specified in the overlay is loaded to the FPGA using the FPGA manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) specified in the region. If FPGA programming succeeds, the bridges are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reenabled and the overlay makes it into the live device tree. The child devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) are then populated. If FPGA programming fails, the bridges are left disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) and the overlay is rejected. The overlay's ranges property maps the lwhps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) the two child devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) Base tree contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) fpga_mgr: fpga-mgr@ff706000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) compatible = "altr,socfpga-fpga-mgr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = <0xff706000 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0xffb90000 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) interrupts = <0 175 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) fpga_bridge0: fpga-bridge@ff400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) compatible = "altr,socfpga-lwhps2fpga-bridge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg = <0xff400000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) resets = <&rst LWHPS2FPGA_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clocks = <&l4_main_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) fpga_region0: fpga-region0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) compatible = "fpga-region";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fpga-mgr = <&fpga_mgr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) fpga_bridge1: fpga-bridge@ff500000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) compatible = "altr,socfpga-hps2fpga-bridge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg = <0xff500000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) resets = <&rst HPS2FPGA_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clocks = <&l4_main_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) Overlay contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /dts-v1/ /plugin/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fragment@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) target = <&fpga_region0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __overlay__ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) firmware-name = "soc_system.rbf";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) fpga-bridges = <&fpga_bridge1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ranges = <0x20000 0xff200000 0x100000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) <0x0 0xc0000000 0x20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) gpio@10040 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) compatible = "altr,pio-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg = <0x10040 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) altr,ngpio = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clocks = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) onchip-memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) compatible = "altr,onchipmem-15.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reg = <0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) Supported Use Models
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) uses are specific to a FPGA device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * No FPGA Bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) In this case, the FPGA Manager which programs the FPGA also handles the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bridges behind the scenes. No FPGA Bridge devices are needed for full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) reconfiguration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Full reconfiguration with hardware bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) In this case, there are hardware bridges between the processor and FPGA that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) need to be controlled during full reconfiguration. Before the overlay is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FPGA Region. The FPGA Region is the child of the bridge that allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) register access to the FPGA. Additional bridges may be listed in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) fpga-bridges property in the FPGA region or in the device tree overlay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Partial reconfiguration with bridges in the FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) In this case, the FPGA will have one or more PRR's that may be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) separately while the rest of the FPGA can remain active. To manage this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) bridges need to exist in the FPGA that can gate the buses going to each FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) region while the buses are enabled for other sections. Before any partial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reconfiguration can be done, a base FPGA image must be loaded which includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PRR's with FPGA bridges. The device tree should have a FPGA region for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PRR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) Device Tree Examples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) The intention of this section is to give some simple examples, focusing on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) the placement of the elements detailed above, especially:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * FPGA Bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * FPGA Region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * target-path or target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) For the purposes of this section, I'm dividing the Device Tree into two parts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) each with its own requirements. The two parts are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * The live DT prior to the overlay being added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * The DT overlay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) to handle programming the FPGA. If the FPGA Region is the child of another FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) they are specified in the FPGA Region by the "fpga-bridges" property. During
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FPGA programming, the FPGA Region will disable the bridges that are in its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "fpga-bridges" list and will re-enable them after FPGA programming has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) succeeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) The Device Tree Overlay will contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * "target-path" or "target"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) The insertion point where the the contents of the overlay will go into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) live tree. target-path is a full path, while target is a phandle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * "ranges"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) The address space mapping from processor to FPGA bus(ses).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * "firmware-name"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) Specifies the name of the FPGA image file on the firmware search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) path. The search path is described in the firmware class documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * "partial-fpga-config"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) This binding is a boolean and should be present if partial reconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) is to be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * child nodes corresponding to hardware that will be loaded in this region of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) Device Tree Example: Full Reconfiguration without Bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) =========================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) Live Device Tree contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fpga_mgr0: fpga-mgr@f8007000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) compatible = "xlnx,zynq-devcfg-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg = <0xf8007000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) interrupts = <0 8 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clocks = <&clkc 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clock-names = "ref_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) syscon = <&slcr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) fpga_region0: fpga-region0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) compatible = "fpga-region";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fpga-mgr = <&fpga_mgr0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #address-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #size-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DT Overlay contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /dts-v1/ /plugin/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fragment@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) target = <&fpga_region0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __overlay__ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) firmware-name = "zynq-gpio.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) gpio1: gpio@40000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) compatible = "xlnx,xps-gpio-1.00.a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) reg = <0x40000000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #gpio-cells = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) xlnx,gpio-width= <0x6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) Device Tree Example: Full Reconfiguration to add PRR's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ======================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) The base FPGA Region is specified similar to the first example above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) This example programs the FPGA to have two regions that can later be partially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) configured. Each region has its own bridge in the FPGA fabric.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DT Overlay contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /dts-v1/ /plugin/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) fragment@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) target = <&fpga_region0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) __overlay__ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) firmware-name = "base.rbf";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) fpga-bridge@4400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) compatible = "altr,freeze-bridge-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) reg = <0x4400 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) fpga_region1: fpga-region1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) compatible = "fpga-region";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #address-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #size-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fpga-bridge@4420 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) compatible = "altr,freeze-bridge-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) reg = <0x4420 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fpga_region2: fpga-region2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) compatible = "fpga-region";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #address-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #size-cells = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) Device Tree Example: Partial Reconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) This example reprograms one of the PRR's set up in the previous example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) The sequence that occurs when this overlay is similar to the above, the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) differences are that the FPGA is partially reconfigured due to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "partial-fpga-config" boolean and the only bridge that is controlled during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) programming is the FPGA based bridge of fpga_region1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /dts-v1/ /plugin/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fragment@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) target = <&fpga_region1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __overlay__ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) firmware-name = "soc_image2.rbf";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) partial-fpga-config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gpio@10040 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) compatible = "altr,pio-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reg = <0x10040 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clocks = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) altr,ngpio = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #gpio-cells = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) Constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ===========
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) It is beyond the scope of this document to fully describe all the FPGA design
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) constraints required to make partial reconfiguration work[1] [2] [3], but a few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) deserve quick mention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) A persona must have boundary connections that line up with those of the partion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) or region it is designed to go into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) During programming, transactions through those connections must be stopped and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) the connections must be held at a fixed logic level. This can be achieved by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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