^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Altera SOCFPGA FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : should contain "altr,socfpga-fpga-mgr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg : base address and size for memory mapped io.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - The first index is for FPGA manager register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - The second index is for writing FPGA configuration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupts : interrupt for the FPGA Manager device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) hps_0_fpgamgr: fpgamgr@ff706000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) compatible = "altr,socfpga-fpga-mgr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) reg = <0xFF706000 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 0xFFB90000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) interrupts = <0 175 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };