Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Altera SOCFPGA Arria10 FPGA Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : should contain "altr,socfpga-a10-fpga-mgr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg        : base address and size for memory mapped io.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)                - The first index is for FPGA manager register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)                - The second index is for writing FPGA configuration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - resets     : Phandle and reset specifier for the device's reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clocks     : Clocks used by the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	fpga_mgr: fpga-mgr@ffd03000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		compatible = "altr,socfpga-a10-fpga-mgr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		reg = <0xffd03000 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		       0xffcfe400 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		clocks = <&l4_mp_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		resets = <&rst FPGAMGR_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	};