^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Altera SoCFPGA ECC Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The ECC Manager counts and corrects single bit errors and counts/handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) double bit errors which are uncorrectable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Cyclone5 and Arria5 ECC Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible : Should be "altr,socfpga-ecc-manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #address-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #size-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - ranges : standard definition, should translate from local addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Subcomponents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) L2 Cache ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - compatible : Should be "altr,socfpga-l2-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - reg : Address and size for ECC error interrupt clear registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) interrupt. Note the rising edge type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) On Chip RAM ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible : Should be "altr,socfpga-ocram-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg : Address and size for ECC error interrupt clear registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - iram : phandle to On-Chip RAM definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) interrupt. Note the rising edge type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) eccmgr: eccmgr@ffd08140 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) compatible = "altr,socfpga-ecc-manager";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) l2-ecc@ffd08140 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) compatible = "altr,socfpga-l2-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) reg = <0xffd08140 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) interrupts = <0 36 1>, <0 37 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ocram-ecc@ffd08144 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) compatible = "altr,socfpga-ocram-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = <0xffd08144 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) iram = <&ocram>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) interrupts = <0 178 1>, <0 179 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Arria10 SoCFPGA ECC Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) The Arria10 SoC ECC Manager handles the IRQs for each peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) in a shared register instead of individual IRQs like the Cyclone5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) and Arria5. Therefore the device tree is different as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - compatible : Should be "altr,socfpga-a10-ecc-manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - altr,sysgr-syscon : phandle to Arria10 System Manager Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) containing the ECC manager registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - #address-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - #size-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - #interrupt-cells : must be set to 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - ranges : standard definition, should translate from local addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Subcomponents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) L2 Cache ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - compatible : Should be "altr,socfpga-a10-l2-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - reg : Address and size for ECC error interrupt clear registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) On-Chip RAM ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - compatible : Should be "altr,socfpga-a10-ocram-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) Ethernet FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) - compatible : Should be "altr,socfpga-eth-mac-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) - altr,ecc-parent : phandle to parent Ethernet node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) NAND FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) - compatible : Should be "altr,socfpga-nand-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - altr,ecc-parent : phandle to parent NAND node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DMA FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) - compatible : Should be "altr,socfpga-dma-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) - altr,ecc-parent : phandle to parent DMA node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) USB FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) - compatible : Should be "altr,socfpga-usb-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - altr,ecc-parent : phandle to parent USB node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) QSPI FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) - compatible : Should be "altr,socfpga-qspi-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) - altr,ecc-parent : phandle to parent QSPI node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) interrupt, in this order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SDMMC FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) - compatible : Should be "altr,socfpga-sdmmc-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) - altr,ecc-parent : phandle to parent SD/MMC node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) - interrupts : Should be single bit error interrupt, then double bit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) interrupt, in this order for port A, and then single bit error interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) then double bit error interrupt in this order for port B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) eccmgr: eccmgr@ffd06000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) compatible = "altr,socfpga-a10-ecc-manager";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) altr,sysmgr-syscon = <&sysmgr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) <0 0 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) l2-ecc@ffd06010 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) compatible = "altr,socfpga-a10-l2-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg = <0xffd06010 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) <32 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ocram-ecc@ff8c3000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) compatible = "altr,socfpga-a10-ocram-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg = <0xff8c3000 0x90>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) <33 IRQ_TYPE_LEVEL_HIGH> ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) emac0-rx-ecc@ff8c0800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) compatible = "altr,socfpga-eth-mac-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) reg = <0xff8c0800 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) altr,ecc-parent = <&gmac0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) <36 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) emac0-tx-ecc@ff8c0c00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) compatible = "altr,socfpga-eth-mac-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg = <0xff8c0c00 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) altr,ecc-parent = <&gmac0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) <37 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) nand-buf-ecc@ff8c2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) compatible = "altr,socfpga-nand-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg = <0xff8c2000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) altr,ecc-parent = <&nand>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) <43 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) nand-rd-ecc@ff8c2400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) compatible = "altr,socfpga-nand-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg = <0xff8c2400 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) altr,ecc-parent = <&nand>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) <45 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) nand-wr-ecc@ff8c2800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) compatible = "altr,socfpga-nand-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg = <0xff8c2800 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) altr,ecc-parent = <&nand>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) <44 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dma-ecc@ff8c8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) compatible = "altr,socfpga-dma-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg = <0xff8c8000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) altr,ecc-parent = <&pdma>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) <42 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) usb0-ecc@ff8c8800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) compatible = "altr,socfpga-usb-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg = <0xff8c8800 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) altr,ecc-parent = <&usb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) <34 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) qspi-ecc@ff8c8400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) compatible = "altr,socfpga-qspi-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reg = <0xff8c8400 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) altr,ecc-parent = <&qspi>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) <46 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) sdmmc-ecc@ff8c2c00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) compatible = "altr,socfpga-sdmmc-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg = <0xff8c2c00 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) altr,ecc-parent = <&mmc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) <47 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) <16 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) <48 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) Stratix10 SoCFPGA ECC Manager (ARM64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) in a shared register similar to the Arria10. However, Stratix10 ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) requires access to registers that can only be read from Secure Monitor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) with SMC calls. Therefore the device tree is slightly different. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) that only 1 interrupt is sent in Stratix10 because the double bit errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) are treated as SErrors in ARM64 instead of IRQs in ARM32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) - compatible : Should be "altr,socfpga-s10-ecc-manager"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) - altr,sysgr-syscon : phandle to Stratix10 System Manager Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) containing the ECC manager registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) - #interrupt-cells : must be set to 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) - #address-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) - #size-cells: must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) - ranges : standard definition, should translate from local addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) Subcomponents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SDRAM ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) - compatible : Should be "altr,sdram-edac-s10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) On-Chip RAM ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) - compatible : Should be "altr,socfpga-s10-ocram-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) - altr,ecc-parent : phandle to parent OCRAM node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) Ethernet FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) - compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) - altr,ecc-parent : phandle to parent Ethernet node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) NAND FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) - compatible : Should be "altr,socfpga-s10-nand-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) - altr,ecc-parent : phandle to parent NAND node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DMA FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) - compatible : Should be "altr,socfpga-s10-dma-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) - altr,ecc-parent : phandle to parent DMA node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) USB FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) - compatible : Should be "altr,socfpga-s10-usb-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) - altr,ecc-parent : phandle to parent USB node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) - interrupts : Should be single bit error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) SDMMC FIFO ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) - compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) - reg : Address and size for ECC block registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) - altr,ecc-parent : phandle to parent SD/MMC node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) - interrupts : Should be single bit error interrupt for port A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) and then single bit error interrupt for port B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) eccmgr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) compatible = "altr,socfpga-s10-ecc-manager";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) altr,sysmgr-syscon = <&sysmgr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) interrupts = <0 15 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) sdramedac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) compatible = "altr,sdram-edac-s10";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ocram-ecc@ff8cc000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) compatible = "altr,socfpga-s10-ocram-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg = <ff8cc000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) altr,ecc-parent = <&ocram>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) emac0-rx-ecc@ff8c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) compatible = "altr,socfpga-s10-eth-mac-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg = <0xff8c0000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) altr,ecc-parent = <&gmac0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) emac0-tx-ecc@ff8c0400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) compatible = "altr,socfpga-s10-eth-mac-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) reg = <0xff8c0400 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) altr,ecc-parent = <&gmac0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) nand-buf-ecc@ff8c8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) compatible = "altr,socfpga-s10-nand-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reg = <0xff8c8000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) altr,ecc-parent = <&nand>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) nand-rd-ecc@ff8c8400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) compatible = "altr,socfpga-s10-nand-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg = <0xff8c8400 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) altr,ecc-parent = <&nand>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) nand-wr-ecc@ff8c8800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) compatible = "altr,socfpga-s10-nand-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg = <0xff8c8800 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) altr,ecc-parent = <&nand>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dma-ecc@ff8c9000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) compatible = "altr,socfpga-s10-dma-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg = <0xff8c9000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) altr,ecc-parent = <&pdma>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) usb0-ecc@ff8c4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) compatible = "altr,socfpga-s10-usb-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) reg = <0xff8c4000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) altr,ecc-parent = <&usb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sdmmc-ecc@ff8c8c00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) compatible = "altr,socfpga-s10-sdmmc-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) reg = <0xff8c8c00 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) altr,ecc-parent = <&mmc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) <15 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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