Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Aspeed AST2500 SoC EDAC node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) correction check).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The memory controller supports SECDED (single bit error correction, double bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) error detection) and single bit error auto scrubbing by reserving 8 bits for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) every 64 bit word (effectively reducing available memory to 8/9).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Note, the bootloader must configure ECC mode in the memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - compatible: should be "aspeed,ast2500-sdram-edac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reg:        sdram controller register set should be <0x1e6e0000 0x174>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts: should be AVIC interrupt #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	edac: sdram@1e6e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		compatible = "aspeed,ast2500-sdram-edac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0x1e6e0000 0x174>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		interrupts = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	};