^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * APM X-Gene SoC EDAC node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) EDAC node is defined to describe on-chip error detection and correction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The follow error types are supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) memory controller - Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) L3 - L3 cache controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) SoC - SoC IP's such as Ethernet, SATA, and etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) The following section describes the EDAC DT node binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - compatible : Shall be "apm,xgene-edac".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - regmap-efuse : Regmap of the PMD efuse resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - regmap-rb : Regmap of the register bus resource. This property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) is optional only for compatibility. If the RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) error conditions are not cleared, it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) continuously generate interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - reg : First resource shall be the CPU bus (PCP) resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) IRQ(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Required properties for memory controller subnode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - compatible : Shall be "apm,xgene-edac-mc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - reg : First resource shall be the memory controller unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) (MCU) resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - memory-controller : Instance number of the memory controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Required properties for PMD subnode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - compatible : Shall be "apm,xgene-edac-pmd" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "apm,xgene-edac-pmd-v2".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - reg : First resource shall be the PMD resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - pmd-controller : Instance number of the PMD controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Required properties for L3 subnode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - compatible : Shall be "apm,xgene-edac-l3" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "apm,xgene-edac-l3-v2".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - reg : First resource shall be the L3 EDAC resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Required properties for SoC subnode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "apm,xgene-edac-l3-soc" for general value reporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - reg : First resource shall be the SoC EDAC resource.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) csw: csw@7e200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) compatible = "apm,xgene-csw", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) reg = <0x0 0x7e200000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mcba: mcba@7e700000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) compatible = "apm,xgene-mcb", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg = <0x0 0x7e700000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mcbb: mcbb@7e720000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) compatible = "apm,xgene-mcb", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reg = <0x0 0x7e720000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) efuse: efuse@1054a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) compatible = "apm,xgene-efuse", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg = <0x0 0x1054a000 0x0 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rb: rb@7e000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) compatible = "apm,xgene-rb", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = <0x0 0x7e000000 0x0 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) edac@78800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "apm,xgene-edac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap-csw = <&csw>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) regmap-mcba = <&mcba>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regmap-mcbb = <&mcbb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) regmap-efuse = <&efuse>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regmap-rb = <&rb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = <0x0 0x78800000 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) interrupts = <0x0 0x20 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) <0x0 0x21 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) <0x0 0x27 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) edacmc@7e800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) compatible = "apm,xgene-edac-mc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg = <0x0 0x7e800000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) memory-controller = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) edacpmd@7c000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) compatible = "apm,xgene-edac-pmd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg = <0x0 0x7c000000 0x0 0x200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pmd-controller = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) edacl3@7e600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible = "apm,xgene-edac-l3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = <0x0 0x7e600000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) edacsoc@7e930000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) compatible = "apm,xgene-edac-soc-v1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg = <0x0 0x7e930000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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