Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * ZTE ZX296702 DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "zte,zx296702-dma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Should contain one interrupt shared by all channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #dma-cells: see dma.txt, should be 1, para number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - dma-channels: physical channels supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - dma-requests: virtual channels supported, each virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		have specific request line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: clock required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	dma: dma-controller@09c00000{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		compatible = "zte,zx296702-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		reg = <0x09c00000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		clocks = <&topclk ZX296702_DMA_ACLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		dma-channels = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		dma-requests = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Use specific request line passing from dmax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) For example, spdif0 tx channel request line is 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	spdif0: spdif0@b004000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#sound-dai-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "zte,zx296702-spdif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg = <0x0b004000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		clocks = <&lsp0clk ZX296702_SPDIF0_DIV>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		clock-names = "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		dmas = <&dma 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		dma-names = "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	}