^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Texas Instruments eDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The eDMA3 consists of two components: Channel controller (CC) and Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Controller(s) (TC). The CC is the main entry for DMA users since it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) responsible for the DMA channel handling, while the TCs are responsible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) execute the actual DMA tansfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) eDMA3 Channel Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible: Should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) AM33xx and AM43xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) channel controller(s) on 66AK2G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #dma-cells: Should be set to <2>. The first number is the DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) number and the second is the TC the channel is serviced on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - reg: Memory map of eDMA CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg-names: "edma3_cc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - ti,tptcs: List of TPTCs associated with the eDMA in the following form:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) <&tptc_phandle TC_priority_number>. The highest priority is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SoC-specific Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) --------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - ti,hwmods: Name of the hwmods associated to the eDMA CC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) The following are mandatory properties for 66AK2G SoCs only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - power-domains:Should contain a phandle to a PM domain provider node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) and an args specifier containing the device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) value. This property is as per the binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) these channels will be SW triggered channels. See example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) the driver, they are allocated to be used by for example the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DSP. See example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - dma-channel-mask: Mask of usable channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Single uint32 for EDMA with 32 channels, array of two uint32 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) EDMA with 64 channels. See example and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Documentation/devicetree/bindings/dma/dma-common.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) eDMA3 Transfer Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - compatible: Should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) AM33xx and AM43xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) transfer controller(s) on 66AK2G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - reg: Memory map of eDMA TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - interrupts: Interrupt number for TCerrint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SoC-specific Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) --------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - ti,hwmods: Name of the hwmods associated to the eDMA TC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) The following are mandatory properties for 66AK2G SoCs only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - power-domains:Should contain a phandle to a PM domain provider node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) and an args specifier containing the device id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) value. This property is as per the binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) - interrupt-names: "edma3_tcerrint"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) edma: edma@49000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "ti,edma3-tpcc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ti,hwmods = "tpcc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = <0x49000000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg-names = "edma3_cc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) interrupts = <12 13 14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dma-requests = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #dma-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Channel 20 and 21 is allocated for memcpy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ti,edma-memcpy-channels = <20 21>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* The following PaRAM slots are reserved: 35-44 and 100-109 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* The following channels are reserved: 35-44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma-channel-mask = <0xffffffff /* Channel 0-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0xffffe007>; /* Channel 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) edma_tptc0: tptc@49800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) compatible = "ti,edma3-tptc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ti,hwmods = "tptc0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg = <0x49800000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) interrupts = <112>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) interrupt-names = "edm3_tcerrint";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) edma_tptc1: tptc@49900000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) compatible = "ti,edma3-tptc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ti,hwmods = "tptc1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg = <0x49900000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) interrupts = <113>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupt-names = "edm3_tcerrint";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) edma_tptc2: tptc@49a00000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) compatible = "ti,edma3-tptc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ti,hwmods = "tptc2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = <0x49a00000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) interrupts = <114>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) interrupt-names = "edm3_tcerrint";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sham: sham@53100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) compatible = "ti,omap4-sham";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ti,hwmods = "sham";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = <0x53100000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) interrupts = <109>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* DMA channel 36 executed on eDMA TC0 - low priority queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dmas = <&edma 36 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dma-names = "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mcasp0: mcasp@48038000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) compatible = "ti,am33xx-mcasp-audio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ti,hwmods = "mcasp0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) reg = <0x48038000 0x2000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) <0x46000000 0x400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg-names = "mpu", "dat";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) interrupts = <80>, <81>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) interrupt-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dmas = <&edma 8 2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) <&edma 9 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) edma1: edma@2728000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg = <0x02728000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg-names = "edma3_cc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) interrupt-names = "edma3_ccint", "emda3_mperr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "edma3_ccerrint";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dma-requests = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #dma-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * memcpy is disabled, can be enabled with:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * ti,edma-memcpy-channels = <12 13 14 15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * for example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) power-domains = <&k2g_pds 0x4f>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) edma1_tptc0: tptc@27b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg = <0x027b0000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) power-domains = <&k2g_pds 0x4f>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) edma1_tptc1: tptc@27b8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) reg = <0x027b8000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) power-domains = <&k2g_pds 0x4f>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mmc0: mmc@23000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) reg = <0x23000000 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dmas = <&edma1 24 0>, <&edma1 25 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ti,needs-special-reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) no-1-8-v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) max-frequency = <96000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) power-domains = <&k2g_pds 0xb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clock-names = "fck", "mmchsdb_fck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) - compatible : "ti,edma3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) - #dma-cells: Should be set to <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) Clients should use a single channel number per DMA request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) - reg: Memory map for accessing module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) - interrupts: Exactly 3 interrupts need to be specified in the order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 1. Transfer completion interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 2. Memory protection interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 3. Error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) - ti,hwmods: Name of the hwmods associated to the EDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) - ti,edma-xbar-event-map: Crossbar event to channel map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) Deprecated properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) Listed here in case one wants to boot an old kernel with new DTB. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) properties might need to be added to the new DTS files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) - ti,edma-regions: Number of regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) - ti,edma-slots: Number of slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) - dma-channels: Specify total DMA channels per CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) edma: edma@49000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) reg = <0x49000000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) interrupts = <12 13 14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) compatible = "ti,edma3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ti,edma-xbar-event-map = /bits/ 16 <1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 2 13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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