Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Texas Instruments DMA Crossbar (DMA request router)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible:	"ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 		"ti,am335x-edma-crossbar" for AM335x and AM437x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg:		Memory map for accessing module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #dma-cells:	Should be set to to match with the DMA controller's dma-cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - dma-requests:	Number of DMA requests the crossbar can receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - dma-masters:	phandle pointing to the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) The DMA controller node need to have the following poroperties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - dma-requests:	Number of DMA requests the controller can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - ti,dma-safe-map: Safe routing value for unused request lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		when mapping xbar input to DMA request, they are either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		allocated to be used by for example the DSP or they are used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		memcpy channels in eDMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) the DMA event number as crossbar ID (input to the DMA crossbar).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) the event should be assigned and <1> is the mux selection for in the crossbar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) When mux 0 is used the DMA channel can be requested directly from edma node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) sdma: dma-controller@4a056000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	compatible = "ti,omap4430-sdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	reg = <0x4a056000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	interrupts =	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	dma-channels = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	dma-requests = <127>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* DMA crossbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sdma_xbar: dma-router@4a002b78 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	compatible = "ti,dra7-dma-crossbar";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	reg = <0x4a002b78 0xfc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	dma-requests = <205>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	ti,dma-safe-map = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* Protect the sDMA request ranges: 10-14 and 100-126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	ti,reserved-dma-request-ranges = <10 5>, <100 27>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	dma-masters = <&sdma>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DMA client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) uart1: serial@4806a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	compatible = "ti,omap4-uart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	reg = <0x4806a000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	ti,hwmods = "uart1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	clock-frequency = <48000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	/* Requesting crossbar input 49 and 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };