^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * DMA40 DMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: "stericsson,dma40"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: Address range of the DMAC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg-names: Names of the above areas to use during resource look-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupt: Should contain the DMAC interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - #dma-cells: must be <3>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - memcpy-channels: Channels to be used for memcpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - dma-channels: Number of channels supported by hardware - if not present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) the driver will attempt to obtain the information from H/W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - disabled-channels: Channels which can not be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) dma: dma-controller@801c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "stericsson,db8500-dma40", "stericsson,dma40";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = <0x801C0000 0x1000 0x40010000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) reg-names = "base", "lcpa";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) interrupts = <0 25 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #dma-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) memcpy-channels = <56 57 58 59 60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) disabled-channels = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) dma-channels = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - dmas: Comma separated list of dma channel requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - dma-names: Names of the aforementioned requested channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Each dmas request consists of 4 cells:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 1. A phandle pointing to the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2. Device signal number, the signal line for single and burst requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) connected from the device to the DMA40 engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 3. The DMA request line number (only when 'use fixed channel' is set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 4. A 32bit mask specifying; mode, direction and endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [NB: This list will grow]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x00000001: Mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Logical channel when unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) Physical channel when set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x00000002: Direction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Memory to Device when unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Device to Memory when set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x00000004: Endianness:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Little endian when unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Big endian when set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x00000008: Use fixed channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Use automatic channel selection when unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Use DMA request line number when set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x00000010: Set channel as high priority:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Normal priority when unset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) High priority when set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bidirectional, i.e. the same for RX and TX operations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0: SPI controller 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1: SD/MMC controller 0 (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 2: SD/MMC controller 1 (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 3: SD/MMC controller 2 (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 4: I2C port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 5: I2C port 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 6: I2C port 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 7: I2C port 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 8: Synchronous Serial Port SSP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 9: Synchronous Serial Port SSP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 10: Multi-Channel Display Engine MCDE RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 11: UART port 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 12: UART port 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 13: UART port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 14: Multirate Serial Port MSP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 15: I2C port 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 16: USB OTG in/out endpoints 7 & 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 17: USB OTG in/out endpoints 6 & 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 18: USB OTG in/out endpoints 5 & 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 19: USB OTG in/out endpoints 4 & 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 20: SLIMbus or HSI channel 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 21: SLIMbus or HSI channel 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 22: SLIMbus or HSI channel 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 23: SLIMbus or HSI channel 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 24: Multimedia DSP SXA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 25: Multimedia DSP SXA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 26: Multimedia DSP SXA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 27: Multimedia DSP SXA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 28: SD/MM controller 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 29: SD/MM controller 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 31: MSP port 0 or SLIMbus channel 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 32: SD/MM controller 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 33: SPI controller 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 34: i2c3 RX2 TX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 35: SPI controller 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 36: USB OTG in/out endpoints 3 & 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 37: USB OTG in/out endpoints 2 & 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 38: USB OTG in/out endpoints 1 & 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 39: USB OTG in/out endpoints 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 40: SPI controller 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 41: SD/MM controller 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 42: SD/MM controller 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 43: SD/MM controller 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 44: Multimedia DSP SXA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 45: Multimedia DSP SXA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 46: SLIMbus channel 8 or Multimedia DSP SXA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 47: SLIMbus channel 9 or Multimedia DSP SXA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 48: Crypto Accelerator 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 50: Hash Accelerator 1 TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 51: memcpy TX (to be used by the DMA driver for memcpy operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 52: SLIMbus or HSI channel 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 53: SLIMbus or HSI channel 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 54: SLIMbus or HSI channel 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 55: SLIMbus or HSI channel 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 56: memcpy (to be used by the DMA driver for memcpy operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 57: memcpy (to be used by the DMA driver for memcpy operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 58: memcpy (to be used by the DMA driver for memcpy operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 59: memcpy (to be used by the DMA driver for memcpy operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 60: memcpy (to be used by the DMA driver for memcpy operations)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 61: Crypto Accelerator 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 63: Hash Accelerator 0 TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uart@80120000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) compatible = "arm,pl011", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = <0x80120000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) interrupts = <0 11 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) <&dma 13 0 0x0>; /* Logical - MemToDev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dma-names = "rx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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