Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * CSR SiRFSoC DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) See dma.txt first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible: Should be "sirf,prima2-dmac", "sirf,atlas7-dmac" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   "sirf,atlas7-dmac-v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - interrupts: Should contain one interrupt shared by all channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #dma-cells: must be <1>. used to represent the number of integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     cells in the dmas property of client device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks: clock required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) dmac0: dma-controller@b00b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	compatible = "sirf,prima2-dmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	reg = <0xb00b0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	interrupts = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	clocks = <&clks 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Fill the specific dma request line in dmas. In the below example, spi0 read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) channel request line is 9 of the 2nd dma controller, while write channel uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) dma controller, while write channel uses 13 of the 1st dma controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) spi0: spi@b00d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	compatible = "sirf,prima2-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	dmas = <&dmac1 9>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		<&dmac1 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) spi1: spi@b0170000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	compatible = "sirf,prima2-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	dmas = <&dmac0 12>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		<&dmac0 13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };