Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Actions Semi Owl SoCs DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   The OWL DMA is a general-purpose direct memory access controller capable of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - $ref: "dma-controller.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       - actions,s900-dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)       - actions,s700-dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)       controller supports 4 interrupts, which are freely assignable to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       DMA channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)     maxItems: 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   "#dma-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)   dma-channels:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)     maximum: 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)   dma-requests:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)     maximum: 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)       Phandle and Specifier of the clock feeding the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)   power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   - "#dma-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   - dma-channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   - dma-requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)     dma: dma-controller@e0260000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)         compatible = "actions,s900-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)         reg = <0xe0260000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)         #dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)         dma-channels = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)         dma-requests = <46>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)         clocks = <&clock 22>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)     };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ...