Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Mediatek UART APDMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: The base address of the APDMA register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: A single interrupt specifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  One interrupt per dma-requests, or 8 if no dma-requests property is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - dma-requests: The number of DMA channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks : Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-names: The APDMA clock for register accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - mediatek,dma-33bits: Present if the DMA requires support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	apdma: dma-controller@11000400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "mediatek,mt2712-uart-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			     "mediatek,mt6577-uart-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0 0x11000400 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		      <0 0x11000480 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		      <0 0x11000500 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		      <0 0x11000580 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		      <0 0x11000600 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		      <0 0x11000680 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		      <0 0x11000700 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		      <0 0x11000780 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		      <0 0x11000800 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		      <0 0x11000880 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		      <0 0x11000900 0 0x80>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		      <0 0x11000980 0 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			     <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			     <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			     <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			     <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		dma-requests = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		clocks = <&pericfg CLK_PERI_AP_DMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		clock-names = "apdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		mediatek,dma-33bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};