Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek High-Speed DMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ==================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) This device follows the generic DMA bindings defined in dma/dma.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible:	Must be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		  "mediatek,mt7622-hsdma": for MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		  "mediatek,mt7623-hsdma": for MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg:		Should contain the register's base address and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts:	Should contain a reference to the interrupt used by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clocks:	Should be the clock specifiers corresponding to the entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		clock-names property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names:	Should contain "hsdma" entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - power-domains: Phandle to the power domain that the device is part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #dma-cells: 	The length of the DMA specifier, must be <1>. This one cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		in dmas property of a client device represents the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)         hsdma: dma-controller@1b007000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "mediatek,mt7623-hsdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		reg = <0 0x1b007000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&ethsys CLK_ETHSYS_HSDMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clock-names = "hsdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DMA clients must use the format described in dma/dma.txt file.