Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * MARVELL MMP DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Marvell Peripheral DMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Used platforms: pxa688, pxa910, pxa3xx, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: Should be "marvell,pdma-1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - interrupts: Either contain all of the per-channel DMA interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		or one irq for pdma device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #dma-channels: Number of DMA channels supported by the controller (defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   to 32 when not specified)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #dma-requests: Number of DMA requestor lines supported by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   (defaults to 32 when not specified)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "marvell,pdma-1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Each channel has specific irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * ICU parse out irq channel from ICU register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * while DMA controller may not able to distinguish the irq channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * Using this method, interrupt-parent is required as demuxer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * 18~21 is ADMA irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pdma: dma-controller@d4000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	      compatible = "marvell,pdma-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	      reg = <0xd4000000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	      interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	      interrupt-parent = <&intcmux32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	      #dma-channels = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)       };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * One irq for all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * Dmaengine driver (DMA controller) distinguish irq channel via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * parsing internal register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) pdma: dma-controller@d4000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	      compatible = "marvell,pdma-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	      reg = <0xd4000000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	      interrupts = <47>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	      #dma-channels = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)       };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Marvell Two Channel DMA Controller used specifically for audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Used platforms: pxa688, pxa910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) - compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) - interrupts: Either contain all of the per-channel DMA interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		or one irq for dma device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "marvell,adma-1.0" used on pxa688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "marvell,pxa910-squ" used on pxa910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* each channel has specific irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) adma0: dma-controller@d42a0800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	      compatible = "marvell,adma-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	      reg = <0xd42a0800 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	      interrupts = <18 19>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	      interrupt-parent = <&intcmux32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)       };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* One irq for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) squ: dma-controller@d42a0800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	      compatible = "marvell,pxa910-squ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	      reg = <0xd42a0800 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	      interrupts = <46>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)       };