Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Milbeaut AXI DMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Milbeaut AXI DMA controller has only memory to memory transfer capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) * DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: 	Should be  "socionext,milbeaut-m10v-xdmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg:		Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: 	Should contain all of the per-channel DMA interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)                 Number of channels is configurable - 2, 4 or 8, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                 the number of interrupts specified should be {2,4,8}.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #dma-cells: 	Should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	xdmac0: dma-controller@1c250000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		compatible = "socionext,milbeaut-m10v-xdmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		reg = <0x1c250000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		interrupts = <0 17 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			     <0 18 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			     <0 19 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			     <0 20 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	};