Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Milbeaut AHB DMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Milbeaut AHB DMA controller has transfer capability below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - device to memory transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  - memory to device transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible:       Should be  "socionext,milbeaut-m10v-hdmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg:              Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts:       Should contain all of the per-channel DMA interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)                      Number of channels is configurable - 2, 4 or 8, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                      the number of interrupts specified should be {2,4,8}.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #dma-cells:       Should be 1. Specify the ID of the slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clocks:           Phandle to the clock used by the HDMAC module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	hdmac1: dma-controller@1e110000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		compatible = "socionext,milbeaut-m10v-hdmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		reg = <0x1e110000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		interrupts = <0 132 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			     <0 133 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			     <0 134 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			     <0 135 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			     <0 136 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			     <0 137 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			     <0 138 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			     <0 139 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		clocks = <&dummy_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	};