Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) NXP LPC18xx/43xx DMA MUX (DMA request router)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible:	"nxp,lpc1850-dmamux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg:		Memory map for accessing module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - #dma-cells:	Should be set to <3>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 		* 1st cell contain the master dma request signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 		* 2nd cell contain the mux value (0-3) for the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 		* 3rd cell contain either 1 or 2 depending on the AHB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 		  master used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - dma-requests:	Number of DMA requests for the mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - dma-masters:	phandle pointing to the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The DMA controller node need to have the following poroperties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - dma-requests:	Number of DMA requests the controller can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) dmac: dma@40002000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	arm,primecell-periphid = <0x00041080>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	reg = <0x40002000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	interrupts = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	clocks = <&ccu1 CLK_CPU_DMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	clock-names = "apb_pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	#dma-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	dma-channels = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	dma-requests = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	lli-bus-interface-ahb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	lli-bus-interface-ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	mem-bus-interface-ahb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	mem-bus-interface-ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	memcpy-burst-size = <256>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	memcpy-bus-width = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dmamux: dma-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	compatible = "nxp,lpc1850-dmamux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	#dma-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	dma-requests = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	dma-masters = <&dmac>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) uart0: serial@40081000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	compatible = "nxp,lpc1850-uart", "ns16550a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	reg = <0x40081000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	reg-shift = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	interrupts = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	clock-names = "uartclk", "reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	dmas = <&dmamux 1 1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		&dmamux 2 1 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };