Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Hisilicon K3 DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) See dma.txt first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible: Must be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) -              "hisilicon,k3-dma-1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) -              "hisilicon,hisi-pcm-asp-dma-1.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: Should contain one interrupt shared by all channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #dma-cells: see dma.txt, should be 1, para number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - dma-channels: physical channels supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - dma-requests: virtual channels supported, each virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		have specific request line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: clock required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		dma0: dma@fcd02000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			compatible = "hisilicon,k3-dma-1.0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			reg = <0xfcd02000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			dma-channels = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 			dma-requests = <27>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			interrupts = <0 12 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 			clocks = <&pclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Use specific request line passing from dmax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) For example, i2c0 read channel request line is 18, while write channel use 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		i2c0: i2c@fcb08000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			compatible = "snps,designware-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			dmas =	<&dma0 18          /* read channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				 &dma0 19>;        /* write channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		i2c1: i2c@fcb09000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			compatible = "snps,designware-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			dmas =	<&dma0 20          /* read channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				 &dma0 21>;        /* write channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)