Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * IMG Multi-threaded DMA Controller (MDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Must be "img,pistachio-mdc-dma".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Must contain the base address and length of the MDC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Must contain all the per-channel DMA interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks: Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   See ../clock/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clock-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - sys: MDC system interface clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - img,cr-periph: Must contain a phandle to the peripheral control syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   node which contains the DMA request to channel mapping registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   The maximum burst size is this value multiplied by the hardware-reported bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - #dma-cells: Must be 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   - The first cell is the peripheral's DMA request line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - The second cell is a bitmap specifying to which channels the DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     line may be mapped (i.e. bit N set indicates channel N is usable).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   - The third cell is the thread ID to be used by the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - dma-channels: Number of supported DMA channels, up to 32.  If not specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   the number reported by the hardware is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) mdc: dma-controller@18143000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	compatible = "img,pistachio-mdc-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	reg = <0x18143000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		     <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		     <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		     <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		     <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		     <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		     <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		     <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		     <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		     <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		     <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		     <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clocks = <&system_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clock-names = "sys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	img,max-burst-multiplier = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	img,cr-periph = <&cr_periph>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	#dma-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) spi@18100f00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };