Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) NXP Layerscape SoC qDMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ==================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) This device follows the generic DMA bindings defined in dma/dma.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible:		Must be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 			 "fsl,ls1021a-qdma": for LS1021A Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 			 "fsl,ls1028a-qdma": for LS1028A Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			 "fsl,ls1043a-qdma": for ls1043A Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			 "fsl,ls1046a-qdma": for ls1046A Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg:			Should contain the register's base address and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupts:		Should contain a reference to the interrupt used by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupt-names:	Should contain interrupt names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 			 "qdma-queue0": the block0 interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			 "qdma-queue1": the block1 interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			 "qdma-queue2": the block2 interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			 "qdma-queue3": the block3 interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			 "qdma-error":  the error interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - fsl,dma-queues:	Should contain number of queues supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - dma-channels:	Number of DMA channels supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - block-number:	the virtual block number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - block-offset:	the offset of different virtual block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - status-sizes:	status queue size of per virtual block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - queue-sizes:		command queue size of per virtual block, the size number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			based on queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - dma-channels:		Number of DMA channels supported by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - big-endian:		If present registers and hardware scatter/gather descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			of the qDMA are implemented in big endian mode, otherwise in little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	qdma: dma-controller@8390000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			compatible = "fsl,ls1021a-qdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			      <0x0 0x8389000 0x0 0x1000>, /* Status regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			      <0x0 0x838a000 0x0 0x2000>; /* Block regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			interrupt-names = "qdma-error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 				"qdma-queue0", "qdma-queue1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			dma-channels = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			block-number = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			block-offset = <0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			fsl,dma-queues = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			status-sizes = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			queue-sizes = <64 64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			big-endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DMA clients must use the format described in dma/dma.txt file.