^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "fsl,imx25-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "fsl,imx51-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "fsl,imx53-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "fsl,imx6q-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "fsl,imx7d-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "fsl,imx8mq-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "fsl,imx8mm-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "fsl,imx8mn-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "fsl,imx8mp-sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) The -to variants should be preferred since they allow to determine the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) correct ROM script addresses needed for the driver to work without additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg : Should contain SDMA registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - interrupts : Should contain SDMA interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - #dma-cells : Must be <3>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) The first cell specifies the DMA request/event ID. See details below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) about the second and third cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) scripts firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The second cell of dma phandle specifies the peripheral type of DMA transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) The full ID of peripheral types can be found below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ID transfer type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ---------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0 MCU domain SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 1 Shared SSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 2 MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 3 SDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 4 MCU domain UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 5 Shared UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 6 FIRI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 7 MCU domain CSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 8 Shared CSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 9 SIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 10 ATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 11 CCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 12 External peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 13 Memory Stick Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 14 Shared Memory Stick Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 15 DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 16 Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 17 FIFO type Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 18 SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 19 IPU Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 20 ASRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 21 ESAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 22 SSI Dual FIFO (needs firmware ver >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 23 Shared ASRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 24 SAI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) The third cell specifies the transfer priority as below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ID transfer priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0 High
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1 Medium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 2 Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) - gpr : The phandle to the General Purpose Register (GPR) node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <reg shift val>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg is the GPR register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) shift is the bit position inside the GPR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val is the value of the bit (0 or 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sdma@83fb0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = <0x83fb0000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) interrupts = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #dma-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) fsl,sdma-ram-script-name = "sdma-imx51.bin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DMA clients connected to the i.MX SDMA controller must use the format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) described in the dma.txt file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ssi2: ssi@70014000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg = <0x70014000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) interrupts = <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clocks = <&clks 49>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dmas = <&sdma 24 1 0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <&sdma 25 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) fsl,fifo-depth = <15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) Using the fsl,sdma-event-remap property:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) If we want to use SDMA on the SAI1 port on a MX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &sdma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gpr = <&gpr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* SDMA events remap for SAI1_RX and SAI1_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) The fsl,sdma-event-remap property in this case has two values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) - <0 15 1> means that the offset is 0, so GPR0 is the register of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Setting bit 15 to 1 selects SAI1_RX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) - <0 16 1> means that the offset is 0, so GPR0 is the register of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) Setting bit 16 to 1 selects SAI1_TX.
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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