Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Atmel Extensible Direct Memory Access Controller (XDMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) * XDMA Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible: Should be "atmel,sama5d4-dma" or "microchip,sam9x60-dma".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts: Should contain DMA interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - #dma-cells: Must be <1>, used to represent the number of integer cells in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) the dmas property of client devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - The 1st cell specifies the channel configuration register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     - bit 13: SIF, source interface identifier, used to get the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)     interface identifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)     - bit 14: DIF, destination interface identifier, used to get the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)     interface identifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)     - bit 30-24: PERID, peripheral identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) dma1: dma-controller@f0004000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	compatible = "atmel,sama5d4-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	reg = <0xf0004000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	interrupts = <50 4 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	#dma-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * DMA clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DMA clients connected to the Atmel XDMA controller must use the format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) described in the dma.txt file, using a one-cell specifier for each channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) The two cells in order are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 1. A phandle pointing to the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 2. Channel configuration register. Configurable fields are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)     - bit 13: SIF, source interface identifier, used to get the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     interface identifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)     - bit 14: DIF, destination interface identifier, used to get the peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)     interface identifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   - bit 30-24: PERID, peripheral identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) i2c2: i2c@f8024000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	compatible = "atmel,at91sam9x5-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	reg = <0xf8024000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	interrupts = <34 4 6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	dmas = <&dma1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		 | AT91_XDMAC_DT_PERID(6))>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	       <&dma1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		| AT91_XDMAC_DT_PERID(7))>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };