Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Atmel Direct Memory Access Controller (DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "atmel,<chip>-dma".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Should contain DMA registers location and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: Should contain DMA interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #dma-cells: Must be <2>, used to represent the number of integer cells in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) the dmas property of client devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) dma0: dma@ffffec00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	compatible = "atmel,at91sam9g45-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	reg = <0xffffec00 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	interrupts = <21>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	#dma-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) DMA clients connected to the Atmel DMA controller must use the format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) described in the dma.txt file, using a three-cell specifier for each channel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) a phandle plus two integer cells.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) The three cells in order are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 1. A phandle pointing to the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 2. The memory interface (16 most significant bits), the peripheral interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) (16 less significant bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 3. Parameters for the at91 DMA configuration register which are device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) dependent:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   - bit 7-0: peripheral identifier for the hardware handshaking interface. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   identifier can be different for tx and rx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) i2c0@i2c@f8010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	compatible = "atmel,at91sam9x5-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	reg = <0xf8010000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	interrupts = <9 4 6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	dmas = <&dma0 1 7>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	       <&dma0 1 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };