Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * ARM PrimeCells PL080 and PL081 and derivatives DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: "arm,pl080", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	      "arm,pl081", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	      "faraday,ftdmac020", "arm,primecell"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   in the hardware and must be specified here as <0x0003b080>. This number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   follows the PrimeCell standard numbering using the JEP106 vendor code 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   for Faraday Technology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg: Address range of the PL08x registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupt: The PL08x interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks: The clock running the IP core clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names: Must contain "apb_pclk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #dma-cells: must be <2>. First cell should contain the DMA request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)               second cell should contain either 1 or 2 depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)               which AHB master that is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - dma-channels: contains the total number of DMA channels supported by the DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - dma-requests: contains the total number of DMA requests supported by the DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   64, 128 or 256 bytes are legal values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   values, the Faraday FTDMAC020 can also accept 64 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - dmas: List of DMA controller phandle, request channel and AHB master id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - dma-names: Names of the aforementioned requested channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dmac0: dma-controller@10130000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	compatible = "arm,pl080", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	reg = <0x10130000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	interrupt-parent = <&vica>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	interrupts = <15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	clocks = <&hclkdma0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	clock-names = "apb_pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	lli-bus-interface-ahb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	lli-bus-interface-ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	mem-bus-interface-ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	memcpy-burst-size = <256>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	memcpy-bus-width = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	#dma-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) device@40008000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	dmas = <&dmac0 0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		&dmac0 1 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };