Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Applied Micro X-Gene SoC DMA nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) DMA nodes are defined to describe on-chip DMA interfaces in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) APM X-Gene SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties for DMA interfaces:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: Should be "apm,xgene-dma".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - device_type: set to "dma".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: Address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   It contains the information of registers in the following order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   1st - DMA control and status register address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   2nd - Descriptor ring control and status register address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   3rd - Descriptor ring command register address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   4th - Soc efuse register address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupts: DMA has 5 interrupts sources. 1st interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   are completion interrupts for each DMA channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clocks: Reference to the clock entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - dma-coherent : Present if dma operations are coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	dmaclk: dmaclk@1f27c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "apm,xgene-device-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		#clock-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clocks = <&socplldiv2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		reg = <0x0 0x1f27c000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		reg-names = "csr-reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clock-output-names = "dmaclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	dma: dma@1f270000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			compatible = "apm,xgene-storm-dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			device_type = "dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			reg = <0x0 0x1f270000 0x0 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			      <0x0 0x1f200000 0x0 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			      <0x0 0x1b000000 0x0 0x400000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			      <0x0 0x1054a000 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			interrupts = <0x0 0x82 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 				     <0x0 0xb8 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				     <0x0 0xb9 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 				     <0x0 0xba 0x4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 				     <0x0 0xbb 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			dma-coherent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			clocks = <&dmaclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};