^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Freescale MXS LCD Interface (LCDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) New bindings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) =============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Should be "fsl,imx28-lcdif" for i.MX28.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Should be "fsl,imx6sx-lcdif" for i.MX6SX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: Address and length of the register set for LCDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts: Should contain LCDIF interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks: A list of phandle + clock-specifier pairs, one for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) entry in 'clock-names'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names: A list of clock names. For MXSFB it should contain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - "pix" for the LCDIF block clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - (MX6SX-only) "axi", "disp_axi" for the bus interface clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required sub-nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - port: The connection to an encoder chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) lcdif1: display-controller@2220000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) reg = <0x02220000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) <&clks IMX6SX_CLK_LCDIF_APB>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) <&clks IMX6SX_CLK_DISPLAY_AXI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) clock-names = "pix", "axi", "disp_axi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) parallel_out: endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) remote-endpoint = <&panel_in_parallel>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Deprecated bindings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Should be "fsl,imx28-lcdif" for i.MX28.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - reg: Address and length of the register set for LCDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - interrupts: Should contain LCDIF interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - display: phandle to display node (see below for details)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * display node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - bits-per-pixel: <16> for RGB565, <32> for RGB888/666.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - bus-width: number of data lines. Could be <8>, <16>, <18> or <24>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Required sub-node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - display-timings: Refer to binding doc display-timing.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) lcdif@80030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) compatible = "fsl,imx28-lcdif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg = <0x80030000 2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) interrupts = <38 86>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) display: display {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bits-per-pixel = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bus-width = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) display-timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) native-mode = <&timing0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) timing0: timing0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clock-frequency = <33500000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) hactive = <800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) vactive = <480>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) hfront-porch = <164>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) hback-porch = <89>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) hsync-len = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) vback-porch = <23>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) vfront-porch = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) vsync-len = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) hsync-active = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) vsync-active = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) de-active = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pixelclk-active = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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