* Rockchip DMC(Dynamic Memory Controller) device
Required properties:
- compatible: Should be one of the following.
- "rockchip,px30-dmc" - for PX30 SoCs.
- "rockchip,rk1808-dmc" - for RK1808 SoCs.
- "rockchip,rk3128-dmc" - for RK3128 SoCs.
- "rockchip,rk3228-dmc" - for RK3228 SoCs.
- "rockchip,rk3288-dmc" - for RK3288 SoCs.
- "rockchip,rk3308-dmc" - for RK3308 SoCs.
- "rockchip,rk3328-dmc" - for RK3328 SoCs.
- "rockchip,rk3368-dmc" - for RK3368 SoCs.
- "rockchip,rk3399-dmc" - for RK3399 SoCs.
- "rockchip,rk3568-dmc" - for RK3568 SoCs.
- "rockchip,rk3588-dmc" - for RK3588 SoCs.
- "rockchip,rv1126-dmc" - for RV1126 SoCs.
- devfreq-events: Node to get DDR loading, Refer to
Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt
- interrupts: The interrupt number to the CPU. The interrupt specifier format
depends on the interrupt controller. It should be DCF interrupts,
when DDR dvfs finish, it will happen.
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon";
- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
Optional properties:
- ddr_timing: DDR timing need to pass to arm trust firmware
- upthreshold: The upthreshold to simpleondeamnd policy
- downdifferential: The downdifferential to simpleondeamnd policy
- vop-bw-dmc-freq: The property is an array of 3-tuples items, and
each item consists of bandwidth and frequency like
<min-bandwidth max-bandwidth frequency>.
min-bandwidth: minimum ddr bandwidth in Mbyte/sec.
max-bandwidth: maximum ddr bandwidth in Mbyte/sec.
frequency: ddr frequency in KHz.
- #cooling-cells: This property indicates dmc can work as a cooling device
- ddr_power_model: Sets power model parameters.
- dynamic-power-coefficient: A u32 value that represents the running time dynamic
power coefficient in units of mW/MHz/uVolt^2. The coefficient can either be
calculated from power measurements or derived by analysis.
- static-power-coefficient: A u32 value that represents the static power
coefficient.
- ts: An array containing coefficients for the temperature scaling factor.
Used as : tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0], where T = temperature
- thermal-zone: A string identifying the thermal zone used for the dmc
Example:
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <21>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
dram_dll_dis_freq = <300>;
phy_dll_dis_freq = <125>;
ddr3_odt_dis_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_ddr3_odt = <PHY_DRV_ODT_240>;
lpddr3_odt_dis_freq = <333>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_lpddr3_odt = <PHY_DRV_ODT_240>;
lpddr4_odt_dis_freq = <333>;
lpddr4_drv = <LP4_PDDS_60ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
phy_lpddr4_odt = <PHY_DRV_ODT_60>;
};
dmc_opp_table: dmc_opp_table {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <900000>;
};
};
dmc: dmc {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
ddr_timing = <&ddr_timing>;
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
upthreshold = <15>;
downdifferential = <10>;
#cooling-cells = <2>;
ddr_power_model: ddr_power_model {
dynamic-power-coefficient = <120>;
static-power-coefficient = <300>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
}
status = "disabled";
};